The complexity of modern microelectronic circuit designs has given rise to the concept of circuit modeling, whereby transistor-level behaviors may be represented by Hardware Description Language (HDL) constructs, including but not limited to Verilog-A, VHDL, VHDL-AMS, Verilog-AMS, Verilog®, SystemC, and other HDL languages. These behavioral models allow significantly faster simulation times than conventional transistor simulation models (e.g., SPICE™).
Conventional HDL modeling is typically used as part of a standard circuit design flow to provide a representation of circuit behavior.
To better understand various aspects of the embodiments of the invention set forth below, conventional methods for circuit modeling/simulation will now be described.
FIG. 10 shows a conventional method for circuit modeling and simulation. The method is designated by the general reference character 1000, and can include creating a design 1002 and then proceeding to execute a simulation/verification of the design 1004. In undertaking a simulation/verification, a method 1000 can first determine if simulation runtime is an issue 1006. If simulation runtime is not an issue, the design can be simulated at a full transistor level 1008. Time involved in such a simulation is notated as Tsys,tr. That is, a simulation runtime can generally depend upon the number of total transistors contained in the design.
If simulation runtime is an issue, a method 1000 can include modeling each sub-circuit of the overall circuit using an HDL code 1010. In the conventional example of FIG. 10, an HDL can be Verilog, and the circuit can include three sub-circuits A-C. As shown in FIG. 10, sub-circuit HDL models can represent a “typical” behavior. That is, the models will represent circuit behavior at some nominal temperature and power supply level.
Each modeled sub-circuit can be examined to determine if the sub-circuit properly matches a transistor level behavior of the sub-circuit (1012a to 1012c). In the event a model does not match a desired behavior, the model can be modified or substituted with another model (return to step 1010).
Once the sub-circuit HDL models provide the desired behavior, an overall system simulation can be run 1014. That is, a simulation can be run that integrates all sub-circuit models together. As in the case of the sub-circuit models, system level simulation can also represent a “typical” behavior. Time involved in such a simulation is notated as Tsys,mod. That is, a simulation runtime can generally depend upon the number of sub-circuits included in the overall design.
Once a system level simulation has been run, method 1000 also includes determining whether or not variations due to “corners” of a device being modeled/simulated are a concern (step 1016). Corners are understood to be variations that can occur in manufacturing and/or operation of a device. As but a few examples, corners can represent the outside limits, or predetermined points between such limits, of manufacturing variations, operating voltages and/or operating temperatures, and combinations thereof. If corner variations are not a concern, a simulation can be complete (step 1018). If however, corner variations are a concern, the simulation results cannot be considered complete, as the simulation may be too inaccurate (step 1020).
Thus, while a conventional “fast” approach of FIG. 10 can allow for quick simulation of the functionality of a circuit, accuracy can be sacrificed because the models utilized may not reflect deviations in circuit behavior due to changes in fabrication process, supply voltage, and ambient temperature, sometimes referred to as process-voltage-temperature (or “PVT”) corners.
Disadvantages of conventional modeling solutions, like that shown in FIG. 10, can be that simulation results may not be accurate over variations in fabrication processing, temperature, or supply voltage. This can make such models unsuitable for use in verifying that a design can meet predetermined specifications over such corners.
For example, FIG. 11 shows the response of a circuit modeled conventionally. Simulation was performed at three different PVT corner conditions: CORNER COND. 1, CORNER COND. 2 and CORNER COND. 3. As shown, such a model provides no variation in simulation response under such different corner conditions. This may not accurately reflect changes occurring at such corner conditions in an actual circuit (or circuit portion) that is manufactured.
In light of the above, it would be desirable to have a quick and reliable simulation technique for modeling performance of designs over expected variations, such as PVT corners.